Amplitude converting circuit

ABSTRACT

A level shifter includes first and second P type thin film transistors (TFTs) and first and second N type TFTs for latching levels of first and second output nodes, third and fourth N type TFTs for setting levels of the first and second output nodes, and first and second resistance elements and first and second capacitors for applying, between the gate-source of the third and fourth N type TFTs, a voltage higher than a voltage of an input signal, in response to rising and falling edges of the input signal respectively.

TECHNICAL FIELD

The present invention relates to an amplitude converting circuit and,more specifically, to an amplitude converting circuit for convertingamplitude of a signal.

BACKGROUND ART

FIG. 17 is a block diagram representing a configuration of a portionrelated to image display of a conventional portable telephone.

Referring to FIG. 17, the portable telephone includes a control LSI 51,which is an MOST (MOS transistor) type integrated circuit, a levelshifter 52, which is an MOST type integrated circuit, and a liquidcrystal display device 53, which is a TFT (Thin Film Transistor) typeintegrated circuit.

Control LSI 51 generates a control signal for liquid crystal displaydevice 53. The “H” level of this control signal is 3V, and the “L” levelis 0V. Though a number of control signals are generated actually, onlyone control signal will be described here for simplicity. Level shifter52 converts logic level of the control signal from control LSI 51 andgenerates an internal control signal. The “H” level of this internalcontrol signal is 7.5V and the “L” level is 0V. Liquid crystal displaydevice 53 displays images in accordance with the internal control signalfrom level shifter 52.

FIG. 18 is circuit diagram representing a configuration of level shifter52. Referring to FIG. 18,level shifter 52 includes P channel MOStransistors 54, 55 and N channel MOS transistors 56, 57. P channel MOStransistors 54 and 55 are connected between a node N51 of a power supplypotential VCC (7.5V) and output nodes N54 and N55, respectively, withtheir gates connected to output nodes N55 and N54, respectively. Nchannel MOS transistors 56 and 57 are connected between output nodes N54and N55 and a node of the ground potential GND, with their gatesreceiving input signals VI and /VI, respectively.

Assume that the input signals VI and /VI are at the “L” level (0V) and“H” level (3V), respectively, and that the output signals VO and /VO areat the “H” level (7.5V) and the “L” level (0V). At this time, MOStransistors 54 and 57 are conductive, and MOS transistors 55 and 56 arenon-conductive.

In this state, when the input signal VI rises from the “L” level (0V) tothe “H” level (3V) and the input signal /VI falls from the “H” level(3V) to the “L” level (0V), first, N channel MOS transistor 56 isrendered conductive and the potential at node N54 lowers. When thepotential at node N54 becomes lower than a potential that is the powersupply potential VCC minus the absolute value of the threshold voltageof P channel MOS transistor 55, P channel MOS transistor 55 is graduallyrendered conductive, and the potential at node N55 begins to increase.When the potential at node N55 begins to increase, the source-gatevoltage of P channel MOS transistor 54 becomes smaller and theconduction resistance value of P channel MOS transistor 54 becomeshigher, and the potential at output node N54 further lowers. Therefore,the circuit operates in a positive feedback manner, and the levelconverting operation ends when the output nodes VO and /VO attains tothe “L” level (0V) and the “H” level (7.5V), respectively.

FIG. 19 is a circuit diagram representing a configuration of anotherconventional level shifter 60. Referring to FIG. 19, level shifter 60differs from level shifter 52 shown in FIG. 18 in that P channel MOStransistors 61 and 62 are added. P channel MOS transistor 61 is insertedbetween the drain of P channel MOS transistor 54 and output node N54,and receives at its gate the input signal VI. P channel MOS transistor62 is inserted between the drain of P channel MOS transistor 55 andoutput node N55, and receives at its gate the input signal /VI.

In level shifter 60, when the input signal VI rises from the “L” level(0V) to the “H” level (3V), P channel MOS transistor 61 is rendered fromconductive to non-conductive, and the current flowing from node N51 ofthe power supply potential VCC to output node N54 is reduced,facilitating lowering of the potential at output node N54. As a result,P channel MOS transistor 55 is rendered conductive, facilitatingincrease of the potential at output node N55. Thus, operation marginbecomes larger than level shifter 52 of FIG. 18.

As described above, in the conventional level shifters 52 and 60, it isa presupposition of operation that N channel MOS transistor 56 isrendered conductive in response to the rise of the input signal VI fromthe “L” level (0V) to the “H” level (3V). In order for N channel MOStransistor 56 to be rendered conductive, it is necessary that thethreshold potential of N channel MOS transistor 56 is not higher thanthe “H” level (3V) of the input signal VI.

In a general semiconductor LSI, the threshold voltage of a transistorcan easily be set to 3V or lower. A low-temperature polysilicon TFT thatis included in the liquid crystal display device, however, hasconsiderable fluctuation in threshold voltage, and therefore, it isdifficult to set the threshold voltage of the TFT at 3V or lower. Forthis reason, a level shifter 52 or 60 formed by high-breakdown voltageMOS transistors is provided between control LSI 51 and liquid crystaldisplay device 53 to convert logic level of signals.

Provision of such level shifter 52 or 60, however, means addition ofcost of the level shifter 52 or 60 to the system cost, resulting inincreased system cost.

DISCLOSURE OF THE INVENTION

Therefore, a main object of the present invention is to provide anamplitude converting circuit that operates properly even when amplitudevoltage of an input signal is smaller than the threshold voltage of aninput transistor.

The amplitude converting circuit in accordance with the presentinvention converts a first signal of which amplitude is a first voltage,to a second signal of which amplitude is a second voltage higher thanthe first voltage. The amplitude converting circuit includes first andsecond transistors of a first conductivity type, both receiving at theirfirst electrodes the second voltage, having their second electrodesconnected to first and second output nodes to output the second signaland a complementary signal thereof, respectively, and their inputelectrodes connected to the second and first output nodes, respectively,third and fourth transistors of a second conductivity type having theirfirst electrodes connected to the first and second output nodes,respectively, and a driving circuit driven by the first signal and acomplementary signal thereof, applying a third voltage higher than thefirst voltage between the input electrode and the second electrode ofthe third transistor in response to a leading edge of the first signalto render conductive the third transistor, and applying the thirdvoltage between the input electrode and the second electrode of thefourth transistor in response to a trailing edge of the first signal torender conductive the fourth transistor. The third voltage, which ishigher than the first voltage as the amplitude voltage of the fistsignal, is applied between the input electrode and the second electrodeof the third or fourth transistor, in response to a leading edge or atrailing edge of the first signal. Therefore, operation is ensured evenwhen the amplitude voltage of the first signal is lower than thethreshold voltage of the third or fourth transistor,

Preferably, the driving circuit includes a first resistance elementconnected between the input electrode and the second electrode of thethird transistor, a first capacitor having one electrode receiving thecomplementary signal of the first signal and the other electrodeconnected to the input electrode of the third transistor, a secondresistance element connected between the input electrode and the secondelectrode of the fourth transistor, and a second capacitor having oneelectrode receiving the first signal and the other electrode connectedto the input electrode of the fourth transistor, and applies the firstsignal and the complementary signal thereof to the second electrodes ofthe third and the fourth transistors, respectively. Here, the firstvoltage is further applied through the first or the second capacitor tothe input electrode of the third or fourth transistor that has beencharged to the first voltage through the first or the second resistanceelement.

Preferably, the first resistance element includes a fifth transistorconnected between the input electrode and the second electrode of thethird transistor and receiving at its input electrode a fourth voltage.The second resistance element includes a sixth transistor connectedbetween the input electrode and the second electrode of the fourthtransistor and receiving at its input electrode the fourth voltage.Here, only a small area is occupied by the first and second resistanceelements.

Preferably, the fifth and sixth transistors are of the secondconductivity type, and the fourth voltage is equal to the secondvoltage. Thus, only a small number of voltage sources are required.

Preferably, the first resistance element includes a fifth transistorconnected between the input electrode and the second electrode of thethird transistor. The second resistance element includes a sixthtransistor connected between the input electrode and the secondelectrode of the fourth transistor. The driving circuit further includesa pulse generating circuit that raises the resistance value of the fifthtransistor pulse-wise in response to a leading edge of the first signaland raises the resistance value of the sixth transistor pulse-wise inresponse to a trailing edge of the first signal. Thus, lowering of thepotential of the third and fourth transistors can be made moderate.

Preferably, the fifth and sixth transistors are of the secondconductivity type. The pulse generating circuit includes a thirdresistance element connected between a node of a fourth voltage of thesame polarity as the second voltage and the input electrode of the fifthtransistor, a third capacitor having one electrode receiving the firstsignal and the other electrode connected to the input electrode of thefifth transistor, a fourth resistance element connected between the nodeof the fourth voltage and the input electrode of the sixth transistor,and a fourth capacitor having one electrode receiving a complementarysignal of the first signal and the other electrode connected to theinput electrode of the sixth transistor. Here, the input electrode ofthe fifth or sixth transistor charged to the fourth voltage through thethird or fourth resistance element is down-converted by the amount ofthe first voltage, through the third or fourth capacitor.

Preferably, the fourth voltage is equal to the second voltage. Thus,only a small number of voltage sources are required.

Preferably, the fifth and sixth transistors are of the firstconductivity type. The pulse generating circuit includes a thirdresistance element connected between a node of a fourth voltage of anopposite polarity to the second voltage and the input electrode of thefifth transistor, a third capacitor having one electrode receiving acomplementary signal of the first signal and the other electrodeconnected to the input electrode of the fifth transistor, a fourthresistance element connected between the node of the fourth voltage andthe input electrode of the sixth transistor, and a fourth capacitorhaving one electrode receiving the first signal and the other electrodeconnected to the input electrode of the sixth transistor. Here, theinput electrode of the fifth or sixth transistor charged to the fourthvoltage through the third or fourth resistance element is boosted by theamount of the first voltage, through the third or fourth capacitor.

Preferably, the driving circuit further includes a first diode elementconnected between the second electrode and the input electrode of thethird transistor, and a second diode element connected between thesecond electrode and the input electrode of the fourth transistor. Thus,it is possible to quickly charge the input electrode of the third orfourth transistor to the first voltage.

Preferably, the driving circuit includes a first resistance elementconnected between the second electrode of the third transistor and anode of a reference voltage, a first capacitor having one electrodereceiving the first signal and the other electrode connected to thesecond electrode of the third transistor, a second resistance elementconnected between the second electrode of the fourth transistor and thenode of the reference voltage, and a second capacitor having oneelectrode receiving a complementary signal of the first signal and theother electrode connected to the second electrode of the fourthtransistor, and applies the first signal and the complementary signalthereof to the input electrodes of the fourth and third transistors,respectively. Here, the second electrode of the third or fourthtransistor that is set to the reference voltage through the first orsecond resistance element is down-converted by the amount of the secondvoltage, through the first or second capacitor.

Preferably, the first resistance element includes a fifth transistorconnected between the second electrode of the third transistor and anode of a reference voltage. The second resistance element includes asixth transistor connected between the second electrode of the secondtransistor and the node of the reference voltage. The driving circuitfurther includes a pulse generating circuit that raises the resistancevalue of the fifth transistor pulse-wise in response to a leading edgeof the first signal and raises the resistance value of the sixthtransistor pulse-wise in response to a trailing edge of the firstsignal. Here, increase of the voltage at the input electrodes of thethird and fourth transistors can be made moderate.

Preferably, the fifth and sixth transistors are of the secondconductivity type. The pulse generating circuit includes a thirdresistance element connected between a node of a fourth voltage of thesame polarity as the second voltage and the input electrode of the fifthtransistor, a third capacitor having one electrode receiving the firstsignal and the other electrode connected to the input electrode of thefifth transistor, a fourth resistance element connected between the nodeof the fourth voltage and the input electrode of the sixth transistor,and a fourth capacitor having one electrode receiving a complementarysignal of the first signal and the other electrode connected to theinput electrode of the sixth transistor. Thus, the input electrode ofthe fifth or sixth transistor that is charged to the fourth voltagethrough the third or fourth resistance element is down-converted by theamount of the first voltage, through the third or fourth capacitor.

Preferably, the fourth voltage is equal to the second voltage. Thus,only a small number of voltage sources are required.

Preferably, a latch circuit is further provided for latching thepotentials of the first and second output nodes. Thus, the potentials atthe first and second output nodes can be held stably.

Preferably, the latch circuit includes fifth and sixth transistors ofthe second conductivity type, having their first electrodes connected tothe first and second output nodes, respectively, receiving at theirsecond electrodes the first signal and the complementary signal thereof,respectively, and having their input nodes connected to the second andfirst output nodes, respectively. Thus, the latch circuits can be formedin a simple manner.

Preferably, the latch circuit includes fifth and sixth transistors ofthe second conductivity type connected between the first and secondoutput nodes and a node of a reference voltage, respectively, and havingtheir input electrodes connected to the second and first output nodes,respectively. Thus, only a small drivability is required for the firstsignal and the complementary signal thereof.

Preferably, a fifth transistor of the first conductivity type insertedbetween the second electrode of the first transistor and the firstoutput node and having its input electrode connected to the inputelectrode of the third transistor, and a sixth transistor of the firstconductivity type inserted between the second electrode of the secondtransistor and the second output node and having its input electrodeconnected to the input electrode of the fourth transistor are furtherprovided. Here, the current flowing from the node of the second voltageto the first and second output nodes can be reduced, and currentconsumption can be reduced.

Preferably, the first to fourth transistors are thin film transistors.The present invention is particularly effective in this case.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram representing a portion related to imagedisplay of a portable telephone in accordance with a first embodiment ofthe present invention.

FIG. 2 is a circuit diagram of the level shifter shown in FIG. 1.

FIG. 3 is a time chart representing an operation of the level shiftershown in FIG. 2.

FIGS. 4 to 8 are circuit diagrams representing modifications of thefirst embodiment.

FIG. 9 is a circuit diagram representing a configuration of a levelshifter in accordance with a second embodiment of the present invention.

FIG. 10 is a time chart representing an operation of the level shiftershown in FIG. 9.

FIG. 11 is a circuit diagram representing a configuration of a levelshifter in accordance with a third embodiment of the present invention.

FIG. 12 is a time chart representing an operation of the time shiftershown in FIG. 11.

FIG. 13 is a circuit diagram representing a configuration of a levelshifter in accordance with a fourth embodiment of the present invention.

FIG. 14 is a time chart representing an operation of the level shiftershown in FIG. 13.

FIG. 15 is a circuit diagram representing a modification of the fourthembodiment.

FIG. 16 is a time chart representing an operation of the level shiftershown in FIG. 15.

FIG. 17 is a block diagram representing a portion related to imagedisplay of a conventional portable telephone.

FIG. 18 is a circuit diagram representing a configuration of the levelshifter shown in FIG. 17.

FIG. 19 is a circuit diagram representing another conventional levelshifter.

BEST MODES FOR CARRYING OUT THE INVENTION First Embodiment

FIG. 1 is a block diagram representing a configuration of a portionrelated to image display of a portable telephone in accordance with afirst embodiment of the present invention.

Referring to FIG. 1, the portable telephone includes a control LSI 1,which is an MOST type integrated circuit, and a liquid crystal displaydevice 2, which is a TFT type integrated circuit, and liquid crystaldisplay device 2 includes a level shifter 3 and a liquid crystal displayportion 4.

Control LSI 1 outputs a control signal for liquid crystal display device2. The “H” level of the control signal is 3V, and the “L” level is 0V.Though a number of control signals are generated actually, only onecontrol signal will be described here for simplicity. Level shifter 3converts logic level of the control signal from control LSI 1 andgenerates an internal control signal. The “H” level of this internalcontrol signal is 7.5V and the “L” level is 0V. Liquid crystal displayportion 4 displays images in accordance with the internal control signalfrom level shifter 3.

FIG. 2 is a circuit diagram representing a configuration of levelshifter 3. Referring to FIG. 2, level shifter 3 includes P type TFTs5,6, N type TFTs 7 to 10, resistance elements 11, 12 and capacitors 13,14. P type TFTs 5 and 6 are connected between a node N1 of the powersupply potential VCC (7.5V) and output nodes N5 and N6, respectively,with their gates connected to output nodes N6 and N5, respectively.Signals appealing at output nodes N5 and N6 are the output signals VOand /VO of level shifter 3, respectively. N type TFT 7 is connectedbetween output node N5 and an input node N11, with its gate connected tooutput node N6. N type TFT 8 is connected between output node N6 and aninput node N12, with its gate connected to output node N5. Input nodesN11 and N12 receive input signals VI and /VI, respectively. P type TFTs5 and 6 and N type TFTs 7 and 8 constitute latch circuits for latchingthe levels at output nodes N5 and N6.

N type TFT 9 is connected between input node N11 and output node N5,with its gate connected to a node N9. N type TFT 10 is connected betweeninput node N11 and output node N6, with its gate connected to node N10.Resistance element 11 is connected between nodes N9 and N11, whileresistance element 12 is connected between nodes N10 and N12. Capacitor13 is connected between an input node N13 and node N9, and capacitor 14is connected between an input node N14 and node N10. Input nodes N13 andN14 receive input signal /VI and VI, respectively. Resistance element 11and capacitor 13 form a boosting circuit, and resistance element 12 andcapacitor 14 form a boosting circuit.

FIG. 3 is a time chart representing an operation of level shifter 3shown in FIG. 2. Referring to FIG. 3, in the initial state, the inputsignals VI and /VI are set to the “H” level (3V) and “L” level (0V),respectively, and the output signals VO and /VO are set to the “H” level(7.5V) and the “L” level (0V), respectively. At this time, node N9 isset to the same potential as the input signal VI, that is, 3V, byresistance element 11, and node N10 is set to the same potential as theinput signal /VI, that is, 0V, by resistance element 12. Because ofthese potential relations, P type TFT 5 and N type TFT 8 are renderedconductive, and other TFTs 6, 7, 9 and 10 are non-conductive.Specifically, output node N5 receives the power supply potential VCC(7.5V) through P type TFT 5, and output node N6 receives the potential(0V) of the input signal /VI through N type TFT 8.

When the input signal VI falls from the “H” level (3V) to the “L” level(0V) and the input signal /VI rises from the “L” level (0V) to the “H”level (3V) at time point t1, potential change of input signal /VI istransmitted through capacitor 13 to node N9, and the potential of nodeN9 increases to a potential of 3V or higher. The amount of potentialincrease at this time is in most part determined by the ratio betweenthe capacitance value of capacitor 13 and the capacitance value of aparasitic capacitance (not shown) of node N9. When the capacitance valueof capacitor 13 is set to be sufficiently larger than the capacitancevalue of the parasitic capacitance of node N9, node N9 increases nearlyto 6V, double the amplitude voltage (3V) of the input signals VI and/VI.

As the input signal VI falls from the “H” level (3V) to the “L” level(0V) simultaneously with the input signal /VI, charges at node N9 aredischarged through resistance element 11 to node N11. Therefore, thepotential of node N9 increases from 3V to the peak and then lowersgradually to 0V. Here, by appropriately setting the resistance value ofresistance element 11, it becomes possible to maintain the potential ofnode N9 at a prescribed potential not lower than 3V only for aprescribed time period. When the potential of node 9 attains to theprescribed potential, N type TFT 9 is rendered conductive, and thepotential of output node N5 lowers. When the potential of output node N5lowers, P type TFT 6 is rendered conductive and the potential of outputnode N6 increases. Thus, P type TFT 5 is rendered non-conductive, N typeTFT 7 is rendered conductive, and the potential of output node N5rapidly lowers to the “L” level (0V).

Meanwhile, the potential change of the input signal VI from the “H”level (3V) to the “L” level (0V) is transmitted through capacitor 14 tonode N10, and the potential of node N10 lowers from 0V to approximately−3V. There is no influence on the circuit operation, however, as the Ntype TFT 10 has already been rendered non-conductive.

As a result, the output signal VO falls from the “H” level (7.5V) to the“L” level (0V) and the output signal /VO rises from the “L” level (0V)to the “H” level (7.5V), and thus, a logic level conversion from 3V to7.5V is accomplished.

The potentials of nodes N9 and N10 are respectively shifted byresistance elements 11 and 12 to the levels of the input signals VI and/VI as time passes. At time t2, potentials of nodes N9 and N10 are atthe levels of the input signals VI and /VI, respectively. At time t2,when the input signal /VI rises from the “L” level (0V) to the “H” level(3V) and the input signal VI falls from the “H” level (3V) to the “L”level (0V), the circuit operates in a potential relation reverse to thatdescribed above.

In the first embodiment, a voltage (about 6V) higher than the amplitudevoltage (3V) of the input signal VI is generated in response to afalling edge of the input signal VI and applied to gate-source of N typeTFT 9. Therefore, even when the amplitude voltage (3V) of the inputsignal VI is lower than the threshold voltage of N type TFT 9, levelshifter 3 operates. Accordingly, it becomes possible to implement levelshifter 3 and liquid crystal display portion 4 in one liquid crystaldisplay device 2 (TFT type integrated circuit). As compared with theconventional example in which level shifter 52 and liquid crystaldisplay device 53 must be provided separately, the number of componentscan be reduced, and the system cost becomes lower.

Though a power supply current flows transiently during the operation,TFTs 5, 8 and 10 or TFTs 6, 7 and 9 are rendered non-conductive afterthe levels of output nodes N5 and N6 are established, and therefore, DCcurrent does not flow from node N1 of the power supply potential VCC toinput nodes N11 to N14. Therefore, power consumption of the circuit isquite small.

Though TFTs 5 to 10 are used in the first embodiment, MOS transistorsmay be used in place of the TFTs. In that case, operation is ensuredeven when the amplitude of the input signals VI and /VI is smaller thanthe threshold voltage of the MOS transistors.

Though TFTs, which are insulated gate type field effect transistors, areused in the first embodiment, field effect transistors of differenttypes may be used.

Various modifications of the first embodiment will be described in thefollowing. In level shifter 15 shown in FIG. 4, N type TFTs 7 and 8 havetheir sources grounded. In this modification, currents of N type TFTs 7and 8 are caused to flow not to the input nodes N 11 and N 12 but to theline of the ground potential GND, and therefore, only a smalldrivability is required for the input signals VI and /VI.

A level shifter 16 shown in FIG. 5 differs from level shifter 3 shown inFIG. 2 in that P type TFTs 17 and 18 are added. P type TFT 17 isinserted between the drain of P type TFT 5 and node N5, with its gateconnected to node N9. P type TFT 18 is inserted between the drain of Ptype TFT 6 and node N6, with its gate connected to node N10. In thismodification, when the input signal /VI rises from the “L” level (0V) tothe “H” level (3V) (see time t1 of FIG. 3), P type TFT 17 changes fromthe conductive state to the non-conductive state, and suppresses thecurrent flowing from node N1 of the power supply potential VCC to outputnode N5, facilitating lowering of the potential at node N5. As a result,P type transistor N6 is rendered conductive quickly, facilitatingincrease of the potential at node N6. Further, P type TFTs 17 and 18 arerendered non-conductive and the current flowing from node N1 of thepower supply potential to output nodes N5 and N6 is suppressed asdescribed above, and the power consumption can be reduced.

A level shifter 20 shown in FIG. 6 differs from level shifter 3 shown inFIG. 2 in that resistance elements 11 and 12 are replaced by N type TFTs21 and 22, respectively. N type TFT 21 is connected between nodes N9 andN11, and receives at its gate the power supply potential VCC. N type TFT22 is connected between nodes N10 and N12, and receives at its gate thepower supply potential VCC. Each of N type TFTs 21 and 22 operatesequivalently as a resistance element. Resistance value per unitdimension is higher than resistance elements 11 and 12 shown in FIG. 2,and therefore, area occupied by the resistance elements can be reduced.Each of N type TFTs 21 and 22 may be replaced by a P type TFT. In thatcase, however, it is necessary to apply a negative voltage (−7.5V) tothe gate of the P type TFT.

A level shifter 23 shown in FIG. 7 differs from level shifter 16 shownin FIG. 5 in that resistance elements 11 and 12 are replace by N typeTFTs 21 and 22, respectively. Therefore, the present modificationattains both effects of the modification shown in FIG. 5 and themodification shown in FIG. 6.

A level shifter 25 shown in FIG. 8 is provided by adding, to levelshifter 16 shown in FIG. 5, diode elements 26 and 27. Diode element 26is connected between nodes N11 and N9, and diode element 27 is connectedbetween nodes N12 and N14. When the input signal VI rises from the “L”level (0V) to the “H” level (3V), diode element 26 accelerates increaseof the node N9 to the “H” level (3V) (see FIG. 3). Accordingly, when thesignal /VI rises from the “L” level (0V) to the “H” level (3V) nexttime, rise of node N9 to the “H” level (3V) becomes faster, and N typeTFT 9 is rendered conductive quickly. Diode element 27 functions in thesimilar manner with respect to N type TFT 10. Therefore, in thismodification, level change in the output signals VO and /VO with respectto the level change in input signals VI and /VI becomes faster.

Second Embodiment

FIG. 9 is a circuit diagram representing a configuration of a levelshifter 30 in accordance with a second embodiment of the presentinvention, comparable to FIG. 7. Referring to FIG. 9, level shifter 30differs from level shifter 23 shown in FIG. 7 in that resistanceelements 31, 32 and capacitors 33, 34 are added. Resistance element 31is inserted between node N1 of the power supply potential VCC and thegate of N type TFT 21 (node N21), and resistance element 32 is insertedbetween node N1 and the gate of N type TFT 22 (node N22). Capacitor 33is connected between nodes N11 and N21, and capacitor 34 is connectedbetween nodes N 12 and N22.

FIG. 10 is a time chart representing an operation of level shifter 30.Referring to FIG. 10, in the initial state, input signals VI and VI areset to the “H” level (3V) and the “L” level (0V), respectively, and theoutput signals VO and /VO are set to the “H” level (7.5V) and the “L”level (0V), respectively. Nodes N21 and N22 are receiving the powersupply potential VCC (7.5V) through resistance elements 31 and 32,respectively, and hence N type TFTs 21 and 22 are conductive.Accordingly, node N9 is at the same potential as the input signal VI,that is, 3V, and node N10 is at the same potential as the inputsignal/VI, that is, 0V. Because of these potential relations, P typeTFTs 5, 16 and N type TFT 8 are rendered conductive, and other TFTs 6,7, 9, 10 and 17 are non-conductive. Specifically, output node N5receives the power supply potential VCC (7.5V) through P type TFTs 5 and16, and output node N6 receives the potential of the input signal /VI(0V) through N type TFT 8.

When the input signal VI falls from the “H” level (3V) to the “L” level(0V) and the input signal /VI rises from the “L” level (0V) to the “H”level (3V) at time point t1, potential change of input signal /VI istransmitted through capacitor 13 to node N9, and the potential of nodeN9 increases to a potential of 3V or higher. At the same time, thepotential change of the input signal VI is transmitted through capacitor33 to node N29, and the potential of node N21 lowers by about 3V. Whenthe potential of node N21 lowers, a current flows from node N1 throughresistance element 31 to node N21, and node N21 returns to the powersupply potential VCC (7.5V). While node N21 is at a level lower than7.5V, N type TFT 21 has a high resistance value.

Further, when the input signal VI falls from the “H” level (3V) to the“L” level (0V) at time t1, charges at node N9 are discharged through Ntype TFT 21 to node N11. Therefore, the potential at node N9 increasesfrom 3V to the peak and then gradually lowers to 0V.

At this time, the resistance value of N type TFT 21 is kept relativelyhigh only for a prescribed time period, and lowering of the level ofnode N1 becomes moderate as compared with level shifter 23 shown in FIG.7. Thus, conduction time of N type TFT 9 becomes longer, facilitatinglowering of the potential at node N5.

On the side of node N10, when the input signal VI falls from the “H”level (3V) to the “L” level (0V) and the input signal /VI rises from the“L” level (0V) to the “H” level (3V) at time t1, potential change ininput signal /VI is transmitted through capacitor 14 to node N10, andthe potential of node N10 lowers to 0V or lower. At the same time,potential change in the input signal /VI is transmitted throughcapacitor 34 to node N22, and the potential of node N22 increases byabout 3V. When the potential of node N22 increases, a current flows fromnode N22 through resistance element 32 to node N21, and node N22 returnsto the power supply potential VCC (7.5V). While the potential at nodeN22 is higher than 7.5V, N type TFT 22 has a low resistance value.

When the input signal /VI rises from the “L” level (0V) to the “H” level(3V), a current flows from node N12 through N type TFT 22 to node N10.Therefore, the potential of node N10 lowers from 0V to the peak, andthereafter gradually increases to 3V.

Here, the resistance value of N type TFT 22 is kept relatively low onlyfor a prescribed time period, and hence increase of the level of nodeN10 becomes faster than in level shifter 23 shown in FIG. 7. Thus,boosting of node N10 at the next time point t2 is facilitated.

From the foregoing, it follows that the operation margin of levelshifter 30 is larger than that of level shifter 23.

Though resistance elements 31 and 32 have one electrode connected tonode N1 of the power supply potential VCC (7.5V), the one electrode maybe connected to a node of a positive power supply potential differentfrom the power supply potential VCC.

Further, each of resistance elements 31 and 32 may be formed by an Ntype TFT or a P type TFT. A positive potential higher than the powersupply potential VCC may preferably be applied to the gate of the N typeTFT, and a potential lower than the power supply potential VCC maypreferably be applied to the gate of the P type TFT. P type TFTs 16 and17 may be omitted.

Third Embodiment

FIG. 11 is a circuit diagram representing a configuration of a levelshifter 35 in accordance with a third embodiment of the presentinvention, comparable to FIG. 9. Referring to FIG. 11, level shifter 35differs from level shifter 30 shown in FIG. 9 in that N type TFTs 21 and22 are replaced by P type TFTs 36 and 37. P type TFT 36 is connectedbetween nodes N9 and N11, with its gate connected to node N21. P typeTFT 37 is connected between nodes N10 and N12, with its gate connectedto node N22.

Further, resistance element 31 is connected between node N21 and a nodeN31 of a negative power supply potential −VCC (−7.5V). Resistanceelement 32 is connected between node N22 and a node N32 of the negativepower supply potential −VCC (−7.5V). Capacitor 33 is connected betweennodes N13 and N21, and capacitor 34 is connected between nodes N14 andN22.

FIG. 12 is a time chart representing an operation of level shifter 35.Referring to FIG. 12, in the initial state, the input signals VI and /VIare set to the “H” level (3V) and the “L” level (0V), respectively, andthe output signals VO and /VO are set to the “H” level (7.5V) and the“L” level (0V), respectively. Nodes N21 and N22 are receiving thenegative power supply potential −VCC (−7.5V) through resistance elements31 and 32, respectively, and hence P type TFTs 36 and 37 are conductive.Therefore, node N9 is set to the same potential as the input signal VI,that is, 3V, and node N10 is set to the same potential as the inputsignal /VI, that is, 0V. Because of these potential relations, P typeTFTs 5, 16 and N type TFT 8 are rendered conductive, and other TFTs 6,7, 9, 10 and 17 are non-conductive. Specifically, output node N5receives the power supply potential VCC (7.5V) through P type TFTs 5 and16, and output node N6 receives the potential of the input signal /VI(0V) through N type TFT 8.

When the input signal VI falls from the “H” level (3V) to the “L” level(0V) and the input signal /VI rises from the “L” level (0V) to the “H”level (3V) at time t1, potential change in the input signal /VI istransmitted through capacitor 13 to node N9, and the potential at nodeN9 increases to 3V or higher. At the same time, potential change in theinput signal /VI is transmitted through capacitor 33 to node N21, andthe potential of node N21 increases by about 3V. When the potential ofnode N21 increases, a current flows from node N21 through resistanceelement 31 to node N31, and node N21 returns to the negative powersupply potential −VCC (−7.5V). While the potential at node N21 is higherthan −7.5V, the resistance value of P type TFT 36 is high.

Further, when the input signal VI falls from the “H” level (3V) to the“L” level (0V) at time t1, charges at node N9 are discharged through Ptype TFT 36 to node N11. Therefore, the potential at node N9 increasesfrom 3V to the peak, and thereafter lowers gradually to 0V.

At this time, the resistance value of P type TFT 36 is kept relativelyhigh only for a prescribed time period, and hence lowering of the levelof node N9 becomes moderate as compared with level shifter 23 shown inFIG. 7. Accordingly, conduction time of N type TFT 9 becomes longer,facilitating lowering of the potential at node N5.

On the side of node N10, at time, t1, when the input signal VI fallsfrom the “H” level (3V) to the “L” level (0V) and the input signal /VIrises from the “L” level (0V) to the “H” level (3V), potential change inthe input signal VI is transmitted through capacitor 14 to node N10, andthe potential of node N10 lowers to 0V or lower. At the same time,potential change in the input signal VI is transmitted through capacitor34 to node N22, and the potential of node N22 lowers by about 3V. Whenthe potential at node N22 lowers, a current flows from node N32 throughresistance element 32 to node N22, and node N22 returns to the negativepower supply potential −VCC (−7.5V). While the potential at node N22 islower than −7.5V, the resistance value of P type TFT 37 is low.

When the input signal /VI rises from the “L” level (0V) to the “H” level(3V) at time t1, a current flows from node N12 through P type TFT 37 tonode N10. Therefore, the potential at node N10 lowers from 0V to thepeak, and thereafter gradually increases to 3V.

At this time, as the resistance value of P type TFT 37 is keptrelatively low only for a prescribed time period, level of node N10increases faster than in level shifter 23 shown in FIG. 7. Accordingly,boosting of node N10 at the next time point t2 is facilitated.

From the foregoing, it follows that the operation margin of levelshifter 35 is larger than that of level shifter 23.

Each of resistance elements 31 and 32 may be formed by an N type TFT ora P type TFT. A positive potential higher than the positive power supplypotential VCC may preferably be applied to the gate of the N type TFT,and a potential lower than the negative power supply potential −VCC maypreferably be applied to the gate of the P type TFT. P type TFTs 16 and17 may be omitted.

Fourth Embodiment

FIG. 13 is a circuit diagram representing a configuration of levelshifter 40 in accordance with a fourth embodiment of the presentinvention, comparable to FIG. 5.

Referring to FIG. 13, level shifter 40 differs from level shifter 16shown in FIG. 5 in that N type TFTs 7 and 8 have their gates bothgrounded, and that resistance elements 11, 12 and capacitors 13, 14 arereplaced by resistance elements 41, 42 and capacitors 43, 44,respectively.

Capacitor 43 is connected between input node N11 and the source (nodeN41) of N type TFT 9, and capacitor 44 is connected between input nodeN12 and the source (node N42) of N type TFT 10. Resistance elements 41and 42 are connected between respective nodes N41, N42 and the line ofthe ground potential GND. The input signal /VI is applied directly tothe gates of TFTs 9 and 17, and the input signal VI is directly appliedto the gates of TFTs 10 and 18.

FIG. 14 is a time chart representing an operation of level shifter 40.Referring to FIG. 14, in the initial state, the input signals VI and /VIare set to the “H” level (3V) and the “L” level (0V), respectively, andthe output signals VO and /VO are set to the “H” level (7.5V) and the“L” level (0V), respectively. Nodes N41 and N42 are set to the groundpotential GND by resistance elements 41 and 42. Because of thesepotential relations, P type TFTs 5, 17 and N type TFTs 8, 10 arerendered conductive, and other TFTs 6, 7, 9 and 18 are renderednon-conductive. Specifically, output node N5 receives the power supplypotential VCC (7.5V) through P type TFTs 5 and 7, and output node N6receives the ground potential GND (0V) through N type TFT 8.

When the input signal VI falls from the “H” level (3V) to the “L” level(0V) and the input signal /VI rises from the “L” level (0V) to the “H”level (3V) at time t1, potential change in the input signal VI istransmitted through capacitor 43 to node N41, and node N41 lowers to theground potential GND (0V) or lower. The amount of lowering of thepotential is determined by the ratio between the capacitance value ofcapacitor 43 and the capacitance value of the parasitic capacitance (notshown) of node N41. When the capacitance value of capacitor 43 is setsufficiently larger than the capacitance value of the parasiticcapacitance of node N41, the potential of node N41 lowers by theamplitude voltage of the input signal VI, to −3V.

When the potential of node N41 lowers to about −3V, a current flows fromthe line of the ground potential GND through resistance element 41 tonode N 41. Therefore, the potential of node N41 lowers from 0V to thepeak, and thereafter gradually increases to 0V. Here, by appropriatelysetting the resistance value of resistance element 41, it becomespossible to maintain the potential of node N41 at a prescribed potentialnot higher than 0V.

When node N41 attains to the prescribed potential, the gate-sourcevoltage of N type TFT 9 attains to 3V to 6V, so that N type TFT 9 isrendered conductive and the potential at node N5 lowers. When thepotential at node N5 lowers, P type TFT 6 is rendered conductive and thepotential at node N6 increases. In this manner, as P type TFT 5 isrendered non-conductive, N type TFT 7 is rendered conductive, and thepotential at node N5 lowers rapidly to the “L” level (0V).

Meanwhile, potential change in the input signal /VI from the “L” level(0V) to the “H” level (3V) is transmitted through capacitor 44 to nodeN42, and the potential at node N42 increases from 0V to approximately3V. There is no influence to the circuit operation, however, as N typeTFT 10 has already been rendered non-conductive.

As a result, the output signal VO falls from the “H” level (7.5V) to the“L” level (0V) and the output signal /VO rises from the “L” level (0V)to the “H” level (7.5V), and thus, a logic level conversion from 3V to7.5V is accomplished.

Potentials of nodes N 41 and N42 are gradually made closer to the groundpotential GND by resistance elements 41 and 42, respectively, as timepasses, and at time t2, potentials at nodes N41 and N42 areapproximately at the ground potential GND. At time t2, when the inputsignal VI rises from the “L” level (0V) to the “H” level (3V) and theinput signal /VI falls from the “H” level (3V) to the “L” level (0V),the circuit operates in a potential relation reverse to that describedabove.

By the fourth embodiment, effects similar to that of the firstembodiment can be obtained.

Referring to FIG. 15, resistance elements 41 and 42 may be replaced by Ntype TFTs 21 and 22, resistance elements 31 and 32 may be connectedbetween the gates of N type TFTs 21 and 22 (nodes N21, N22) and node N1,and capacitors 33 and 34 may be connected between nodes N11 and N12 andnodes N21 and N22, respectively, as in the second embodiment. Referringto FIG. 16, when the input signal VI falls from the “H” level (3V) tothe “L” level (0V) at time t1, the potential at node N21 lowers by about3V, and is maintained lower than the power supply potential VCC (7.5V)only for a prescribed time period. When the potential of node N21becomes lower than 7.5V, the resistance value of N type TFT 21 becomeshigher. Therefore, the level of node N41 increases moderately ascompared with level shifter 40 shown in FIG. 13, facilitating loweringof output node N5 to the “L” level. Further, when the input signal /VIrises from the “L” level (0V) to the “H” level (3V) at time t1, thepotential at node N22 increases by about 3V, and is maintained higherthan the power supply potential VCC (7.5V) only for a prescribed timeperiod. When the potential of node N21 becomes higher than 7.5V, theresistance value of N type TFT 22 becomes lower. Therefore, the level ofnode N42 lowers faster than in level shifter 40 shown in FIG. 13,facilitating the down-converting operation of node N42 at the next timepoint t2.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1. An amplitude converting circuit converting a first signal, having afirst voltage as an amplitude, to a second voltage, having a secondvoltage as an amplitude, the second voltage being higher than the firstvoltage, the circuit comprising: first and second transistors of a firstconductivity type, receiving at respective first electrodes the secondvoltage, and having second electrodes connected to first and secondoutput nodes for outputting the second signal and a complement of thesecond signal, respectively, and input electrodes connected to thesecond and first output nodes, respectively; third and fourthtransistors of a second conductivity type having first electrodesconnected to the first and second output nodes, respectively; and adriving circuit driven by the first signal and a complement of the firstsignal, applying a third voltage, higher than the first voltage, betweenan input electrode and a second electrode of said third transistor, inresponse to a leading edge of the first signal, to render said thirdtransistor conductive, and applying the third voltage between an inputelectrode and a second electrode of said fourth transistor, in responseto a trailing edge of the first signal, to render said fourth transistorconductive, said driving circuit including a first resistance elementconnected between the input electrode and the second electrode of saidthird transistor, a first capacitor having a first electrode receivingthe complement of the first signal and a second electrode connected tothe input electrode of said third transistor, a second resistanceelement connected between the input electrode and the second electrodeof said fourth transistor, and a second capacitor having a firstelectrode receiving the first signal and a second electrode connected tothe input electrode of said fourth transistor.
 2. The amplitudeconverting circuit according to claim 1, wherein said first resistanceelement includes a fifth transistor connected between the inputelectrode and the second electrode of said third transistor andreceiving at an input electrode a fourth voltage; and said secondresistance element includes a sixth transistor connected between theinput electrode and the second electrode of said fourth transistor andreceiving at an input electrode the fourth voltage.
 3. The amplitudeconverting circuit according to claim 2, wherein said fifth and sixthtransistors are of the second conductivity type; and the fourth voltageis equal to the second voltage.
 4. The amplitude converting circuitaccording to claim 1, wherein said first resistance element includes afifth transistor connected between the input electrode and the secondelectrode of said third transistor; said second resistance elementincludes a sixth transistor connected between the input electrode andthe second electrode of said fourth transistor; and said driving circuitfurther includes a pulse generating circuit generating pulsestemporarily increasing resistance of said fifth transistor in responseto a leading edge of the first signal and temporarily increasingresistance of said sixth transistor in response to a trailing edge ofthe first signal.
 5. The amplitude converting circuit according to claim4, wherein said fifth and sixth transistors are of the secondconductivity type; and said pulse generating circuit includes a thirdresistance element connected between a node at a fourth voltage, havingthe same polarity as the second voltage, and the input electrode of saidfifth transistor, a third capacitor having a first electrode receivingthe first signal and a second electrode connected to the input electrodeof said fifth transistor, a fourth resistance element connected betweenthe node at the fourth voltage and the input electrode of said sixthtransistor, and a fourth capacitor having a first electrode receivingthe complement of the first signal and a second electrode connected tothe input electrode said sixth transistor.
 6. The amplitude convertingcircuit according to claim 5, wherein the fourth voltage is equal to thesecond voltage.
 7. The amplitude converting circuit according to claim4, wherein said fifth and sixth transistors are of the firstconductivity type; and said pulse generating circuit includes a thirdresistance element connected between a node at a fourth voltage, ofpolarity opposite to that of the second voltage, and the input electrodeof said fifth transistor, a third capacitor having a first electrodereceiving the complement of said first signal and a second electrodeconnected to the input electrode of said fifth transistor, a fourthresistance element connected between the node at the fourth voltage andthe input electrode of said sixth transistor, and a fourth capacitorhaving a first electrode receiving the first signal and a secondelectrode connected to the input electrode of said sixth transistor. 8.The amplitude converting circuit according to claim 1, wherein saiddriving circuit further includes a first diode element connected betweenthe second electrode and the input electrode of said third transistor,and a second diode element connected between the second electrode andthe input electrode of said fourth transistor.
 9. The amplitudeconverting circuit according to claim 1, further comprising a latchcircuit for latching potentials of the first and second output nodes.10. The amplitude converting circuit according to claim 9, wherein saidlatch circuit includes fifth and sixth transistors of the secondconductivity type, having first electrodes connected to the first andsecond output nodes, respectively, second electrodes receiving the firstsignal and the complement of the first signal, respectively, and inputelectrodes connected to the second and first output nodes, respectively.11. The amplitude converting circuit according to claim 9, wherein saidlatch circuit includes fifth and sixth transistors of the secondconductivity type, connected between the first and second output nodesand a node at a reference potential, respectively, and having inputelectrodes connected to the second and first output nodes, respectively.12. The amplitude converting circuit according to claim 9, wherein saidfirst, second, third, and fourth transistors are thin film transistors.13. The amplitude converting circuit according to claim 1, furthercomprising: a fifth transistor of the first conductivity type insertedbetween the second electrode of said first transistor and the firstoutput node and having an input electrode connected to the inputelectrode of said third transistor; and a sixth transistor of the firstconductivity type inserted between the second electrode of said secondtransistor and the second output node and having an input electrodeconnected to the input electrode of said fourth transistor.
 14. Theamplitude converting circuit according to claim 1, wherein said first,second, third, and fourth transistors are thin film transistors.
 15. Anamplitude converting circuit converting a first signal, having a firstvoltage as an amplitude, to a second voltage, having a second voltage asan amplitude, the second voltage being higher than the first voltage,the circuit comprising: first and second transistors of a firstconductivity type, receiving at respective first electrodes the secondvoltage, and having second electrodes connected to first and secondoutput nodes for outputting the second signal and a complement of thesecond signal, respectively, and input electrodes connected to thesecond and first output nodes, respectively; third and fourthtransistors of a second conductivity type having first electrodesconnected to the first and second output nodes, respectively; and adriving circuit driven by the first signal and a complement of the firstsignal, applying a third voltage, higher than the first voltage, betweenan input electrode and a second electrode of said third transistor, inresponse to a leading edge of the first signal, to render said thirdtransistor conductive, and applying the third voltage between an inputelectrode and a second electrode of said fourth transistor, in responseto a trailing edge of the first signal, to render said fourth transistorconductive, said driving circuit including a first resistance elementconnected between the second electrode of said third transistor and anode at a reference voltage, a first capacitor having a first electrodereceiving the first signal and a second electrode connected to thesecond electrode of said third transistor, a second resistance elementconnected between the second electrode of said fourth transistor and thenode at the reference voltage, and a second capacitor having a firstelectrode receiving the complement of the first signal and a secondelectrode connected to the second electrode of said fourth transistor.16. The amplitude converting circuit according to claim 15, wherein saidfirst resistance element includes a fifth transistor connected betweenthe second electrode of said third transistor and the node at thereference voltage; said second resistance element includes a sixthtransistor connected between the second electrode of said fourthtransistor and the node at the reference voltage; and said drivingcircuit further includes a pulse generating circuit generating pulsestemporarily increasing resistance of said fifth transistor in responseto leading edge of the first signal and temporarily increasingresistance of said sixth transistor in response to a trailing edge ofthe first signal.
 17. The amplitude converting circuit according toclaim 16, wherein said fifth and sixth transistors are of the secondconductivity type; and said pulse generating circuit includes a thirdresistance element connected between a node at a fourth voltage, havingthe same polarity as the second voltage, and the input electrode of saidfifth transistor, a third capacitor having a first electrode receivingthe first signal and a second electrode connected to the input electrodeof said fifth transistor, a fourth resistance element connected betweenthe node at the fourth voltage and the input electrode of said sixthtransistor, and a fourth capacitor having a first electrode receivingthe complement of the first signal and a second electrode connected tothe input electrode of said sixth transistor.
 18. The amplitudeconverting circuit according to claim 17, wherein the fourth voltage isequal to the second voltage.
 19. The amplitude converting circuitaccording to claim 15, wherein said first, second, third, and fourthtransistors are thin film transistors.
 20. The amplitude convertingcircuit according to claim 15, further comprising a latch circuit forlatching potentials of the first and second output nodes.
 21. Theamplitude converting circuit according to claim 20, wherein said latchcircuit includes fifth and sixth transistors of the second conductivitytype, having first electrodes connected to the first and second outputnodes, respectively, second electrodes receiving the first signal andthe complement of the first signal, respectively, and input electrodesconnected to the second and first output nodes, respectively.
 22. Theamplitude converting circuit according to claim 20, wherein said latchcircuit includes fifth and sixth transistors of the second conductivitytype, connected between the first and second output nodes and a node ata reference potential, respectively, and having input electrodesconnected to the second and first output nodes, respectively.
 23. Theamplitude converting circuit according to claim 15, further comprising:a fifth transistor of the first conductivity type inserted between thesecond electrode of said first transistor and the first output node andhaving an input electrode connected to the input electrode of said thirdtransistor; and a sixth transistor of the first conductivity typeinserted between the second electrode of said second transistor and thesecond output node and having an input electrode connected to the inputelectrode of said fourth transistor.